1. Field of the Invention
The invention relates to a constant voltage circuit supplied with an input voltage from a primary power supply such as a battery for providing an output voltage more stable than the input voltage.
2. Description of the Prior Art
In motor vehicles for example, various electric loads such as a starter motor, a horn, lights and so on are conventionally connected to a DC power supply or battery. Turning on or off such a load sometimes causes a sudden change of more than a few voltages in the supply voltage (i.e., the battery voltage). This is especially true when an engine of a vehicle the battery of which has experienced a secular deterioration is started under a low temperature. Since electric power is not supplied from the alternator to the battery and the voltage of the battery is lowered in such a case, driving the starter motor will cause the voltage of the power supply to the ECU (electronic control unit) for engine control to lower so extremely that the ECU can not work, preventing the engine from start.
For this reason, it is required to reduce the minimum operating voltage of ECU in order to prevent such problems. The reduction of the minimum operating voltage is required not only to the ECU but also to control devices used under the circumstances in which the power supply voltage is apt to change: e.g., other control devices for vehicle-mounted air conditioner and automatic transmission, control units used in portable devices with a built-in battery, etc.
In such control devices or units, in addition to setting the minimum operating voltage low in each of functional circuits constituting the control device or unit, there is provide a constant voltage circuit which is supplied with electric power from an external DC power supply and generating a predetermined constant voltage in order to prevent the functional circuits from malfunctioning with a sudden change in the power supply voltage. The constant voltage circuit supplies power to each functional circuit.
FIG. 1 shows an exemplary arrangement of a type of conventional constant voltage circuits. In FIG. 1, the CV circuit 1 is supplied with a DC voltage Vb from an external DC supply such as a battery (not shown) from a power feeder line and a ground line. The CV circuit 1 comprises a bias circuit 20a and an output bipolar transistor Q1a of NPN type having its base connected to the output of the bias circuit 20a, its collector connected to the power feeder line (or Vb line) and its emitter connected to the load (not shown). The CV circuit 1 is so arranged as to transfer the input voltage Vb to the load as an output voltage Vo through the output transistor Q1a. (In CV circuits with a bipolar output transistor or CV circuits of type I, the portion other than the output bipolar transistor can be considered as a bias circuit for the output transistor.) The bias circuit 20a comprises a constant current circuit 210 for providing a constant current based on the input voltage Vb, a PNP-type transistor Q21 having its base connected to the constant current circuit 210 output, its emitter connected to the Vb line and its collector connected to the base of the output transistor Q1a, and seven serially coupled diodes D1 through D7 having their anode end connected to the collector of transistor Q21 and the base of the output transistor Q1a and their cathode end connected to ground. Since the seven diodes D1 through D7 function as a clamp circuit for limiting the base voltage of transistor Q1a to a clamp voltage equal to the voltage across the seven diodes in the easy flow direction (i.e., 7xc3x970.7=4.9 V in this example), even when the battery voltage Vb becomes high, the output voltage Vo of the CV circuit 1 is limited to a constant voltage; i.e., the difference by subtracting the base-to-emitter voltage Vf (=0.7 V) of transistor Q1a from the clamp voltage (i.e., 4.2 V in this example).
If the battery voltage Vb is in such a range as not to activate the diodes D1 through D7, i.e., the battery voltage Vb is less than 5 (=Vec1+7xc3x970.7), then the output voltage Vo is given by Vbxe2x88x92Vec1xe2x88x92Vf (=Vbxe2x88x920.8) V. Assuming that the minimum voltage required by the load is Vreq, then the input DC voltage or battery voltage has to be not less than Vreq+Vec1+Vf. In other words, the control device including the CV circuit 1 and such the load has a minimum operating voltage of Vreq+Vec1+Vf. In this sense, the voltage drop (Vec1+Vf) in the constant voltage circuit is one of the causes of raising the minimum operating voltage of control devices. The voltage drop in the constant voltage circuit becomes critical with the lowering of the input voltage Vb.
FIG. 2 shows an exemplary arrangement of another type of conventional constant voltage circuits which has an output MOS FET (metaloxide semiconductor field-effect transistor). In FIG. 2, N-channel MOS FET Q1b has its drain connected to the power supply Vb line and its source connected to the load (not shown). The CV circuit 2 further comprises a bias circuit 20b or voltage booster 202 having its output connected to the gate of MOS FET Q1b. When the voltage booster 202 is generating a voltage sufficiently higher than the input or battery voltage Vb, MOS FET Q1b operates in a linear region or on state. In this state (referred to as xe2x80x9cthe completely-on statexe2x80x9d), the source-to-drain voltage of MOS FET Q1b is substantially zero, which causes the input voltage Vb to be supplied as it is to the load. Since the drain loss is small and, accordingly, less heat is generated, the completely-on state is a preferable state for the output MOS FET.
On the other hand, as the voltage booster 202 output or the gate voltage lowers with the lowering of the input voltage Vb, MOS FET Q1b eventually enters into a saturation state. In the saturation state, the drain current decreases and the source-to-drain voltage rises with the gate voltage lowering. In this state (referred to as an xe2x80x9cincompletely-on statexe2x80x9d), the drain loss is larger and, accordingly, more heat is generated, which is an undesirable state for the output MOS FET. In this way, an input voltage lower than the minimum operating voltage of the voltage booster 202 can cause a sudden lowering of the output voltage Vo of the CV circuit 2. (Though the above discussion has been presented in conjunction with a CV circuit having an N-channel MOS FET as the output transistor, the same discussion is applied to a CV circuit having a P-channel MOS FET as the output transistor. CV circuits with an output MOS FET is referred to as xe2x80x9cCV circuits of type IIxe2x80x9d).
As seen from the foregoing, there is a need for a constant voltage circuit robust to the input voltage lowering, i.e., a constant voltage circuit in which the output voltage lowers as little as possible with a lowering of the input voltage.
The above and other problems has been solved in accordance with the present invention which relates to a constant voltage circuit fed with a first voltage through first and second power conductors for supplying a second voltage to a load. A constant voltage circuit comprises an output transistor having a control electrode and having first and second channel electrodes constituting a primary output path to the load. The output transistor has the first channel electrode connected with one of the power conductors, the second channel electrode connected with one end of the load. The other end of the load is connected to the other power conductor that is not connected to the first channel electrode. The constant voltage circuit further comprises a bias circuit for providing a bias voltage to the control electrode to turn on the output transistor and a substitute circuit, responsive to a detection of the lowing of the first voltage to a predetermined voltage, for providing a secondary output path that is connected in parallel with the primary output path. Doing this minimizes the degree of lowering of the second voltage due to the lowering of said first voltage.
The output transistor may be any of NPN and PNP transistors and P-type and N-type MOS FETs.